The present invention generally relates to semiconductor integrated circuits, and more particularly to a bipolar semiconductor integrated circuit.
The integration density of semiconductor integrated circuits is rapidly improving due to the progress in lithography techniques and the like. Hence, the number of signal interconnections within the integrated circuit is increasing, and a region for providing power source interconnections for supplying power source voltages is increasing because of the increase in the power consumption of the integrated circuit. Especially in the case of a bipolar integrated circuit, it is impossible to reduce the current consumption of each circuit below a predetermined value in order to maintain the high-speed operation of each circuit.
In addition, the number of multi-level interconnections is limited to approximately three because deficiencies such as a disconnection and inconsistent thickness of the interconnection are easily generated when four or more levels of interconnections are stacked. Consequently, the chip size becomes large because of the need to increase the signal interconnections in each level and to widen the power source interconnections. Hence, there is a demand to prevent such an increase of the chip size. On the other hand, when the length of the signal interconnection is long, it is impossible to realize a high-speed circuit operation even when high-speed circuit elements are used.
FIGS. 1A and 1B are a plan view and a cross sectional view respectively showing an example of a conventional semiconductor integrated circuit In FIGS. 1A and 1B, a semiconductor chip 12 is accommodated within a stage 11 of a package 10. Terminals 13 for signal input and output and terminals 14 for supplying power source voltages V.sub.CC and V.sub.EE are provided on the semiconductor chip 12, and these terminals 13 and 14 are wire-bonded on package leads 15.
A first power source interconnection (not shown) for the power source voltage V.sub.CC and a second power source interconnection 16 for the power source voltage V.sub.EE are provided on the semiconductor chip 12. The first and second power source interconnections respectively have stripe patterns which intersect each other in the plan view. For example, an emitter coupled logic (ECL) circuit is formed between the first and second power source interconnections.
FIG. 2 shows a cross sectional view of the semiconductor chip 12. As shown in FIG. 2, the semiconductor chip 12 has a p.sup.- -type substrate 21 provided with a metallized layer 20 on a back surface thereof. An n.sup.+ -type buried layer 22, an n-type epitaxial layer 23, a p.sup.+ -type isolation layer 24, a p-type diffusion layer 25 which becomes a base, an n.sup.+ -type diffusion layer 26 which becomes an emitter, an n.sup.+ -type diffusion layer 27 which becomes a collector, and a p-type diffusion layer 28 which becomes a resistor are provided on a front surface of the p.sup.- -type substrate 21. In addition, the semiconductor chip 12 has insulator layers 29 and 30 indicated by hatchings, a first interconnection 31, and a second interconnection 32. For example, the second interconnection 32 corresponds to the second power source interconnection 16 for the power source voltage V.sub.EE shown in FIGS. 1A and 1B.
When considering an integrated circuit with 1000 gates where the current consumption is 1 mA per gate, for example, a current of 1 A flows in total. When the power source interconnection is an aluminum interconnection having a current density of 2.times.10.sup.5 A/cm.sup.2 and a thickness of 1 micron, the power source interconnection needs a large width of 0.5 mm. In addition, there are problems in that a voltage drop caused by the large current flow is large in the power source interconnection having the stripe pattern and that the noise margin of the circuit is poor.
Because of the need to reduce the capacitance between the collector and the substrate, that is, mainly the capacitance introduced between the n.sup.+ -type buried layer 22 and the substrate 21, the substrate 21 has a low impurity density with a high resistivity in the range of 5 .OMEGA.cm to 30 .OMEGA.cm. Normally, the substrate 21 has a thickness of 500 microns, and for this reason, it is impossible to supply the power source voltage from the back surface of the substrate 21 when the voltage drop is taken into account. Thus, the first and second interconnections 31 and 32 are used to supply the power source voltages.
Therefore, the conventional semiconductor integrated circuit suffers problems in that the voltage drop is large due to the long power source interconnections, and the freedom with which the signal interconnections may be designed is limited because the signal interconnections must be positioned avoiding the power source interconnections. In other words, the design flexibility of the interconnection is poor in the conventional integrated circuit. Furthermore, there is another problem in that the chip size becomes large because of the need to provide a large number of terminals for the power source voltages on the semiconductor chip.